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PCI EXPRESS JITTER ATTENUATOR
ICS9DB202
GENERAL DESCRIPTION
The ICS9DB202 is a high perfromance 1-to-2 Differential-to-HCSL Jitter Attenuator designed for use in PCI ExpressTM systems. In some PCI ExpressTM systems, such as those found in desktop PCs, the PCI ExpressTM clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter-attenuating device may be necessary in order to reduce high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS9DB202 has two PLL bandwidth modes. In low bandwidth mode, the PLL loop bandwidth is 500kHz. This setting offers the best jitter attenuation and is still high enough to pass a triangular input spread spectrum profile. In high bandwidth mode, the PLL bandwidth is at 1MHz and allows the PLL to pass more spread spectrum modulation.
FEATURES
* Two 0.7V current mode differential HCSL output pairs * One differential clock input * CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Maximum output frequency: 140MHz * Input frequency range: 90MHz - 140MHz * VCO range: 450MHz - 700MHz * Output skew: 110ps (maximum) * Cycle-to-cycle jitter: 110ps (maximum) * RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 2.42ps (typical) * 3.3V operating supply * 0C to 70C ambient operating temperature * Available in both standard and lead-free RoHS compliant packages * Industrial temperature information available upon request
IC S
HiPerClockSTM
For serdes which have x10 reference multipliers instead of x12.5 multipliers, each of the two PCI ExpressTM outputs (PCIEX0:1) can be set for 125MHz instead of 100MHz by configuring the appropriate frequency select pins (FS0:1).
BLOCK DIAGRAM
IREF
+
Current Set 1 HiZ 0 Enabled
PIN ASSIGNMENT
PLL_BW CLK nCLK FS0 VDD GND PCIEXT0 PCIEXC0 VDD nOE0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDA BYPASS IREF FS1 VDD GND PCIEXT1 PCIEXC1 VDD nOE1
nOE0
nCLK CLK
Phase Detector
Loop Filter
0
VCO
0 /4 1 /5
PCIEXT0 nPCIEXC0
1
ICS9DB202
20-Lead TSSOP 6.50mm x 4.40mm x 0.92 package body G Package Top View
/5 Internal Feedback
FS0
0
0 /5 1 /4
PCIEXT1 nPCIEXC1
ICS9DB202
20-Lead, 209-MIL SSOP 5.30mm x 7.20mm x 1.75mm body package F Package Top View
1
FS1
BYPASS
nOE1
1 HiZ 0 Enabled
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TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5, 9, 12, 16 6, 15 7, 8 10, 11 13, 14 17 18 19 20 Name PLL_BW CLK nCLK FS0 VDD GND PCIEXT0, PCIEXC0 nOE0, nOE1 PCIEXC1, PCIEXT1 FS1 IREF BYPASS VDDA Input Input Input Input Power Power Output Input Output Input Input Power Power Pulldown Type Pullup Description Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.
Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. Pulldown Pullup Frequency select pin. LVCMOS/LVTTL interface levels. Core supply pins. Power supply ground. Differential output pairs. HCSL interface levels. Output enable. When HIGH, forces outputs to HiZ state. When LOW, enables outputs. LVCMOS/LVTTL interface levels. Differential output pairs. HCSL interface levels. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. A fixed precision resistor (475) from this pin to ground provides a reference current used for differential current-mode PCIEX clock outputs. BYPASS pin. When HIGH. bypass mode, when LOW, PLL mode. Pulldown LVCMOS/LVTTL interface levels. Analog supply pin. Requires 24 series resistor.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
TABLE 3A. RATIO OF OUTPUT FREQUENCY TO INPUT FREQUENCY FUNCTION TABLE, FS0
Inputs FS0 0 1 Outputs PCIEX0 5/4 1
TABLE 3B. RATIO OF OUTPUT FREQUENCY TO INPUT FREQUENCY FUNCTION TABLE, FS1
Inputs FS1 0 1 Outputs PCIEX1 1 5/4
TABLE 3C. BYPASS TABLE
Inputs BYPASS 0 1 Mode PLL Mode Bypass Mode (output = inputs)
TABLE 3D. OUTPUT ENABLE FUNCTION TABLE, NOE0
Inputs nOE0 0 1 Outputs PCIEX0 Enabled HiZ
TABLE 3E. OUTPUT ENABLE FUNCTION TABLE, NOE1
Inputs nOE1 0 1 Outputs PCIEX1 Enabled HiZ
TABLE 3F. PLL BANDWIDTH TABLE
Inputs PLL_BW 0 1 Bandwidth 500kHz 1MHz
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO 4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 20 Lead TSSOP 73.2C/W (0 lfpm) 20 Lead SSOP 80.8C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C, RREF = 475
Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3. 3 3. 3 Maximum 3.465 3.465 112 22 Units V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current BYPASS, nOE0, nOE1, FS1 FS0, PLL_BW BYPASS, nOE0, nOE1, FS1 FS0, PLL_BW VDD = VIN = 3.465V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 5 VDD = 3.465V, VIN = 0V A Units mV mV A
IIL
Input Low Current
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C, RREF = 475
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK, nCLK CLK, nCLK Test Conditions VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V 0.15 Minimum Typical Maximum 150 150 1.3 VDD - 0.85 Units A A V V
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
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TABLE 4D. HCSL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C, RREF = 475
Symbol IOH VOH VOL IOZ VOX Parameter Output Current Output High Voltage Output Low Voltage High Impedance Leakage Current Output Crossover Voltage -10 250 Test Conditions Minimum 12 610 Typical 14 Maximum 16 780 65 10 550 Units mA mV mV A mV
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C, RREF = 475
Symbol fMAX Parameter Output Frequency Output Skew; NOTE 1, 2 Cycle-to-Cycle Jitter RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Outputs @ Different Frequencies Outputs @ Same Frequencies Integration Range: 1.5MHz - 22MHz 20% to 80% 300 2.42 1100 52 50 Test Conditions Minimum Typical Maximum 140 110 110 50 Units MHz ps ps ps ps ps %
tsk(o) tjit(cc) tjit(O)
tR / tF
o dc Output Duty Cycle 48 NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot following this section.
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TYPICAL PHASE NOISE AT 100MHZ
0 -10 -20 -30 -40 -50 -60
PCI ExpressTM Filter 100MHz
RMS Phase Jitter (Random) 1.5MHz to 22MHz = 2.42ps (typical)
NOISE POWER dBc Hz
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
Raw Phase Noise Data
5
The illustrated phase noise plot was taken using a low phase noise signal generator, the noise floor of the signal generator is less than that of the device under test. Using this configuration allows one to see the true spectral purity or phase noise performance of the PLL in the device under test.
Phase Noise Result by adding PCI ExpressTM Filter to raw data OFFSET FREQUENCY (HZ)
Due to the tracking ability of a PLL, it will track the input signal up to its loop bandwidth. Therefore, if the input phase noise is greater than that of the PLL, it will increase the output phase noise performance of the device. It is recommended that the phase noise performance of the input is verified in order to achieve the above phase noise performance.
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ICS9DB202 PCI EXPRESS JITTER ATTENUATOR
PARAMETER MEASUREMENT INFORMATION
3.3V5% 3.3V5%
VDD
nCLK VDD VDDA
Qx
SCOPE
CLK
V
PP
Cross Points
V
CMR
HCSL
GND
nQx
GND
0V
3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PCIEXCx PCIEXTy PCIEXCx PCIEXTy
PCIEXC0, PCIEXC1 PCIEXT0, PCIEXT1
tcycle n
tjit(cc) = tcycle n -tcycle n+1
tsk(o)
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
PCIEXC0, PCIEXC1
80% Clock Outputs
80% VSW I N G
PCIEXT0, PCIEXT1
20% tR tF
20%
t PW
t
PERIOD
odc =
t PW t PERIOD
HCSL OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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tcycle n+1
x 100%
ICS9DB202 PCI EXPRESS JITTER ATTENUATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS9DB202 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 24 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin. The 10 resistor can also be replaced by a ferrite bead.
3.3V VDD .01F VDDA .01F 10F 24
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS:
LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kW resistor can be used.
OUTPUTS:
HCSL OUTPUT All unused HCSL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
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RELIABILITY INFORMATION
TABLE 6A. JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP PACKAGE
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98C/W 66.6C/W
500
88C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6B. JAVS. AIR FLOW TABLE FOR 20 LEAD SSOP PACKAGE
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 80.8C/W
200
73.2C/W
500
69.2C/W
TRANSISTOR COUNT
The transistor count for ICS9DB202 is: 2471
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PACKAGE OUTLINE - G SUFFIX
FOR
20 LEAD TSSOP
PACKAGE OUTLINE - F SUFFIX FOR 20 LEAD SSOP
TABLE 6A. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 Millimeters Minimum 20 1.20 0.15 1.05 0.30 0.20 6.60 Maximum
TABLE 6B. PACKAGE DIMENSIONS
Millimeters SYMBOL Minimum N A A1 A2 b c D E E1 e L 0.55 0 -0.05 1.65 0.22 0.09 6.90 7.40 5.0 0.65 BASIC 0.95 8 20 2.0 -1.85 0.38 0.25 7.50 8.20 5.60 Maximum
Reference Document: JEDEC Publication 95, MO-153
Reference Document: JEDEC Publication 95, MO-150
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TABLE 7. ORDERING INFORMATION
Part/Order Number ICS9DB202CG ICS9DB202CGT ICS9DB202CGLF ICS9DB202CGLFT ICS9DB202CF ICS9DB202CFT ICS9DB202CFLF ICS9DB202CFLFT Marking ICS9DB202CG ICS9DB202CG ICS9DB202CGL ICS9DB202CGL ICS9DB202CF ICS9DB202CF ICS9DB202CFLF ICS9DB202CFLF Package 20 Lead TSSOP 20 Lead TSSOP 20 Lead "Lead-Free" TSSOP 20 Lead "Lead-Free" TSSOP 20 Lead SSOP 20 Lead SSOP 20 Lead "Lead-Free" SSOP 20 Lead "Lead-Free" SSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Tube 1000 Tape & Reel Tube 1000 Tape & Reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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REVISION HISTORY SHEET Rev B B B B T7 T4 D Table T4D Page 4 6 8 11 4 1 Description of Change HCSL Table -adjusted VOH min from 680mV to 610mV and added VOH max. Updated HCSL Output Load AC Test Circuit Diagram. Application Information - added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free note. HCSL DC Characteristics - corrected units for VOH & VOL from V to mV. Feature Section - added Input Frequency Range and VCO Range. Date 12/21/04 3/8/06 5/26/06 7/14/06
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www.IDT.com
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For Tech Support
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Corporate Headquarters
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Asia Pacific and Japan
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Europe
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(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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